| US 7,353,313 B2 | ||
| General input/output architecture, protocol and related methods to manage data integrity | ||
| Eric R. Wehage, Tenino, Wash. (US); Jasmin Ajanovic, Portland, Oreg. (US); David Harriman, Portland, Oreg. (US); David M. Lee, Portland, Oreg. (US); Blaise Fanning, El Dorado Hills, Calif. (US); Buck Gremel, Olympia, Wash. (US); Ken Creta, Gig Harbor, Wash. (US); and Wayne Moore, Hillsboro, Oreg. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Oct. 23, 2006, as Appl. No. 11/585,648. | ||
| Prior Publication US 2007/0038793 A1, Feb. 15, 2007 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G06F 13/14 (2006.01) | ||
| U.S. Cl. 710—305 | 24 Claims |
| 1. A method comprising:
receiving a datagram at general input/output (GIO) interface from a remote GIO interface coupled through a GIO link;
validating content of one or more packets embedded within the received datagram by determining whether the one or more packets
meet predetermined framing requirements;
if the framing requirements are met, stripping framing boundaries from the datagram to reveal one or more data link layer
packets; and
issuing an acknowledgment to the remote GIO interface that the datagram was successfully received on positive validation of
the datagram before promoting the embedded data link layer packets to a transaction layer of the GIO interface, wherein the
acknowledgement includes flow control update information to be transmitted to the GIO interface.
|