RUN 2B LEVEL-1 TRIGGER MEETING 15-Feb-02 Update on TAB Progress: John Parsons ----------------------- o ADF Assumptions - 32 chans/board --> 80 boards - neighboring eta-phi TTs grouped o Links from ADF: fast copper o TAB covers 4 eta x 32 phi o Most effort on algorithm implementation - less on interface to outside world o ADF Board (example) - 10 bit ADC - digitize at multiple of BX (4*BX) due to ADC latency . no oversampling . good candidate chip from Burr-Brown: $5 - FPGA to apply FIR . candidate Altera 1K10TC100-2 . run at 60.6 MHz . $10 - output of board = 8-bit Et (serial) . as an example - LSB of signal . voltage scaled of signal from BLS on web . 0.25 GeV LSB - 64 GeV full scale o ADC-to-TAB Links - high bandwidth LVDS serial (channel link from National) . 48:8 serializer/tx . 8:48 rx/deserializer . unit cost $11 - send 8 data bits + clk --> 364 MHz . chipset rated at 672 MHz . Atlas has demonstrated 480 MHz on 20 m cables - problem mapping cables directly from ADF to TAB . 32 chans on ADF doesn't map well to 48 data lines . 512 channels inp to TAB --> 16 cables (don't fit on single-wdith 9U) - --> use data concentrator o Data Concentrator (example) - 3 ADC boards --> 1 Concentrator . at 60.6 MHz of custom P3 backplane - 3 data streams --> 2 LVDS serializers --> 25-pair cable - 6 cables --> TAB - fanout of data to 2 TABs done at this level - **** cable density is an important issue **** . must be resolved soon o TAB - 4x32 on board --> 10 TAB - assume need 5x5 TTs to eval a single TT --> 512 inputs to TAB . (8x32) required - Elements . LVDS Rx . Fanout (8) . Sliding windows chip (8) . Global sums (1) o Fanout FPGA - 64 inp streams (60.6 MHz) --> 128 out streams (90.9 MHz) . 2-fold fanout of signal . change in freq probably better at Sliding Windows chip - pad 8 bit --> 12 bit w/ zero - allows test data to be dowloaded - could use Alter 1K50 ($33) o Sliding Windows - 5x5 --> 128 inputs need per chip - both EM and Jet on same FPGA - bit serial logic at 12*BX = 91 MHz . adds & compares flow at 1 clk tick per operation o EM Algorithm - RoI = 2x2 . 4x4 ring sum & 4x4 H sum for isolation - 7 thresholds possible (output encoded on 3 bits) - 4 channels (3-bits) merged to one 12 bit serial stream . --> output = 4 12-bit serial words o Jet Algorithm - each chip deals with 4x4 (needs 8x8 of input) - RoI = 3x3 EM+H (used for max finding) . Total Energu from 5x5 region - 7 jet threshold possible - output data serialzed like EM - FPGA options . 20K160(-3) ($94): 71% of logic, 0% of mem . 20K200(-3) ($130): 55% of logic, 0% of mem - If need 7x7 region to eval a TT . No. inps 128-->200 . Lcells up by 33% . 20K200: 73% logic used . biggest complication is in the cabling though! o Out of Sliding windows chip (12 bit serial words) - 4 em-data (thresh) - 4 jet-data (thresh) - 4 Et phi-sums - --> 96 bits o Global FPGA to do sums - get Ex, Ey from weighted sums using LUT - this requires high speed --> more expensive chip . 20K160(-1): $264 - "summarizes" EM & jet data to reduce output . this scheme needs to be decided . plenty of logic on chip avail to do this o TAB Latency (from full FPGA simulation) - Fanout 1 BX - Sliding Windows . pipelined logic <1 BX . serialize output 1 BX (pick Trk-match here) - Global FPGA . Ex,Ey calc 1 BX . serialize output 1 BX ----- 5 BX ~ 660 ns - (expect comparable number from ADF) o Global L1Cal Board (1) - from each of 10 TABs . Et, Ex, Ey sums . summarized EM & jet data - calculate Etmiss**2 - AND/OR terms for TFW - no detailed design done yet o Urgent Issues - size of region required for TT (5x5 vs 7x7) . inps/TAB 512-->640 . data fanout 2-->3 (often) . ADF to TAB cabling very different . physics issue is energy sharing (much more likely in 5x5) . decision should be based on simulation . **** this is the priority issue **** - interfaces to Trk-match, L1, L2, L3, SCL . haven't really thought about this much yet . L2: only info it gets is from L1 . TFW worries about synchronization - details of trigger algorithm . less important b/c of flexibility in FPGAs . but large changes may require thought > e.g. tau trigger > should be possible to include this in current FPGAs Denis Calvet: Comments on TAB presentation) ------------- o ADF: cable problems from MSU - I/O should be on rear instead of front panel - cable types - assumed at MSU not enough data density . now looking at AMP cable - could fit 16 of these onto rear mounted cards . would allow suppression of Concentrator cards - need to check these cables with Jamieson Olsen o Could we use denser FPGAs? - include LVDS serializer on chip (Xilinx) - Nevis conclusion: these are very expensive . also power-on problem with Xilinix chips o Including ICR data - ~300 channels - will have some impact on ADF (& TAB cards) - **** important to decide early on this **** o Could also include digital sums on ADF cards - could cut latency for Et sums o Do not foresee to have connection from ADF to outside - TAB must buffer all samples - may be necessary to record inputs to FIR for diagnostics . this is possible locally (but slow & asynch) o SCL interface to TAB - will need to fanout some signals to ADFs o Where to make duplication of data - on ADF or point-to-point within TAB - need to justify the concentrator Denis Calvet: ADF Status ------------- o Sampling freq 4*BX o 10 bit ADC o FIR in Xilinx Virtex chip (integrated LVDS) . could fit 32 FIRs on this chip . speed is on the edge for oversampling o Denis will send comments to mailing list Next Meeting ------------ o 2 weeks from now