| US 7,375,552 B1 | ||
| Programmable logic block with dedicated and selectable lookup table outputs coupled to general interconnect structure | ||
| Steven P. Young, Boulder, Colo. (US); Trevor J. Bauer, Boulder, Colo. (US); Manoj Chirania, Palo Alto, Calif. (US); and Venu M. Kondapalli, Sunnyvale, Calif. (US) | ||
| Assigned to Xilinx, Inc., San Jose, Calif. (US) | ||
| Filed on Jun. 14, 2005, as Appl. No. 11/151,892. | ||
| Int. Cl. H03K 19/177 (2006.01); G06F 7/38 (2006.01) | ||
| U.S. Cl. 326—41 [326/37; 326/38; 326/47] | 11 Claims |
| 1. An integrated circuit, comprising:
an interconnect structure; and
a programmable logic block comprising:
a programmable lookup table (LUT) having a plurality of LUT input terminals coupled to the interconnect structure, a first
LUT output terminal non-programmably coupled to the interconnect structure via a first logic block output terminal, and a
second LUT output terminal;
a first programmable multiplexer having an output terminal coupled to the interconnect structure, a first multiplexer input
terminal coupled to the first LUT output terminal, and a second multiplexer input terminal coupled to the second LUT output
terminal;
a flip-flop having an output terminal coupled to the interconnect structure; and
a second programmable multiplexer, the second programmable multiplexer having an output terminal coupled to a data input terminal
of the flip-flop, a first multiplexer input terminal coupled to the first LUT output terminal, and a second multiplexer input
terminal coupled to the second LUT output terminal.
|