| US 7,385,416 B1 | ||
| Circuits and methods of implementing flip-flops in dual-output lookup tables | ||
| Manoj Chirania, San Jose, Calif. (US); and Martin L. Voogel, Los Altos, Calif. (US) | ||
| Assigned to Xilinx, Inc., San Jose, Calif. (US) | ||
| Filed on Mar. 20, 2007, as Appl. No. 11/726,040. | ||
| Int. Cl. H03K 19/173 (2006.01); H03K 19/177 (2006.01); G06F 7/38 (2006.01) | ||
| U.S. Cl. 326—38 [326/37; 326/40; 716/16] | 18 Claims |
| 1. A flip-flop implemented in a programmable integrated circuit (IC), comprising:
a dual-output lookup table (LUT) having first and second output terminals, the LUT being programmed to implement as a first
function a master latch driving the first output terminal, the LUT being further programmed to implement as a second function
a slave latch driving the second output terminal, wherein:
a first input terminal of the LUT drives the first and second functions and is coupled to the first output terminal of the
LUT;
a second input terminal of the LUT drives the second function and is coupled to the second output terminal of the LUT; and
a third input terminal of the LUT drives the first and second functions and is coupled to provide a clock signal to the flip-flop.
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