`timescale 1ns / 1ns
module main();

reg clk;
initial clk=0;
initial begin
	// $dumpfile("dds.vcd");
	// $dumpvars(5,main);
	forever begin clk=0; #12; clk=1; #13; end
end
reg sync;
initial begin sync=0; #60; sync=1; #11000; $finish; end

reg [13:0] xin=14'b01000000000000;
reg [13:0] yin=14'b00000000000000;
reg [15:0] freq=16'd5000;         // 5000*20 Hz = 100 kHz, 10 us period
wire [13:0] out;
dds d(clk, out, xin, yin, sync, freq, );

reg signed [13:0] out_disp;
always @(negedge clk) begin
	out_disp = out;
	$display("%d %d", $time, out_disp);
end
endmodule