| US 7,376,783 B2 | ||
| Processor system using synchronous dynamic memory | ||
| Kunio Uchiyama, Kodaira (Japan); and Osamu Nishii, Kokubunji (Japan) | ||
| Assigned to Renesas Technology Corp., Tokyo (Japan) | ||
| Filed on Nov. 14, 2006, as Appl. No. 11/598,661. | ||
| Application 11/598661 is a continuation of application No. 10/752569, filed on Jan. 08, 2004, granted, now 7,143,230. | ||
| Application 10/752569 is a continuation of application No. 09/987145, filed on Nov. 13, 2001, granted, now 6,697,908. | ||
| Application 09/987145 is a continuation of application No. 09/520834, filed on Mar. 08, 2000, granted, now 6,334,166. | ||
| Claims priority of application No. 4-249190 (JP), filed on Sep. 18, 1992. | ||
| Prior Publication US 2007/0061537 A1, Mar. 15, 2007 | ||
| Int. Cl. G06F 12/00 (2006.01) | ||
| U.S. Cl. 711—105 | 24 Claims |
| 1. A data processor formed on a single chip comprising:
first address terminals used for multiplexed row and column address to a synchronous memory, the synchronous memory being
operative based on a clock signal inputted from an outside of the synchronous memory;
a processor core;
a main storage controller core coupled with the address terminals, the main storage controller controlling the synchronous
memory; and
a first mode register used to write to a second mode register that resides within the synchronous memory,
wherein the first mode register is assigned to a predetermined address in an address space of the processor core, to be written
a mode register value,
wherein the mode register value stored in the first mode register is outputted from the first address terminals to the synchronous
memory.
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