| US 7,330,357 B2 | ||
| Integrated circuit die/package interconnect | ||
| Gilroy J. Vandentop, Tempe, Ariz. (US); and Hamid R. Azimi, Chandler, Ariz. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Sep. 22, 2003, as Appl. No. 10/667,694. | ||
| Prior Publication US 2005/0063164 A1, Mar. 24, 2005 | ||
| Int. Cl. H05K 7/10 (2006.01); H05K 7/12 (2006.01) | ||
| U.S. Cl. 361—769 [361/770; 361/794] | 4 Claims |
| 1. A device comprising:
an integrated circuit die comprising a first plurality of electrical contacts;
an integrated circuit substrate comprising a second plurality of electrical contacts; and
an interconnect patch comprising a plurality of pliant conductive elements, a first end of one of the plurality of pliant
conductive elements in physical contact with one of the first plurality of electrical contacts and a second end of the one
of the plurality of pliant conductive elements in physical contact with one of the second plurality of electrical contacts.
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