| US 7,382,143 B2 | ||
| Wafer probe interconnect system | ||
| Thomas H. Di Stefano, Monte Sereno, Calif. (US) | ||
| Assigned to Centipede Systems, Inc., San Jose, Calif. (US) | ||
| Filed on Nov. 13, 2006, as Appl. No. 11/559,272. | ||
| Claims priority of provisional application 60/802086, filed on May 18, 2006. | ||
| Prior Publication US 2007/0268031 A1, Nov. 22, 2007 | ||
| Int. Cl. G01R 31/02 (2006.01) | ||
| U.S. Cl. 324—754 | 1 Claim |
| 1. An apparatus for use in testing a plurality of integrated circuit dies in an array, the apparatus comprising:
a plurality of dielectric substrates having a plurality of probe tips protruding from a first surface, wherein the plurality
of probe tips is electrically coupled to a second opposing surface through conductive via plugs;
a plurality of pliant posts coupled to each of the plurality of dielectric substrates, the posts being sufficiently laterally
pliant to allow for thermal expansion of the dielectric substrate without warpage of the dielectric substrate;
a support block coupled to the plurality of pliant posts;
a plurality of printed wiring layers disposed in overlaid sheets and interposed between the plurality of dielectric substrates
and the support block and extending from between rows of said pliant posts, wherein
embedded conductive traces in the printed wiring layers are individually terminated at one end to a via plug and wherein the
flexible sheets are a plurality of flex cables.
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