A New Deep
Sub-micron Readout IC
for the
Tevatron Collider
Brad Krieger
Lawrence Berkeley National Lab
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SVX4 is the new silicon
strip readout IC designed to meet the increased radiation tolerance
requirements (>20 MRad total dose) for Run IIb at the Fermilab Tevatron
collider. The SVX3D design that is currently in use by CDF was migrated from
a 0.8 um radiation-hard process, to a standard deep sub-micron CMOS
technology using “radiation tolerant by design” transistor topologies. Unlike its predecessors, the new design
includes the necessary features required for generic use by both the D0 and
CDF experiments. SVX4 is designed for “dead-timeless” readout, featuring 128
parallel input channels, a 128 x 46-cell analog latency pipeline capable of
buffering up to 4 events, a 128 x 8-bit Wilkinson-type ADC, and a readout
sparsification circuit with 8-bit parallel data I/O via differential
transceivers. The device was designed
and fabricated in the TSMC 0.25 um Mixed-Signal CMOS process using
proprietary radiation-hard standard cells, and full-custom designs. SVX4 is now in pre-production. Details of the design conversion,
integration, and verification process that led to a successful 1st-run
prototype will be discussed, as well as some of the performance highlights. |
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