1. A slew-rate adjusting apparatus for use in a semiconductor memory device, comprising:
a slew-rate modulation signal generator for generating slew-rate modulation signals according to a data signal and the number
of control codes, wherein the slew-rate modulation signal generator includes a logic combination unit for combining logic
levels of the control codes to output control signals and a switching unit for receiving the data signal and the control signals
to generate the slew-rate modulation signals used to adjust a number of switching elements; and
a pre-driver for adjusting a slew rate of an output by changing the number of the switching elements turned on by the slew-rate
modulation signals and the data signal.
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