(a) a differential input stage including

i. a first input transistor having a gate coupled to a first input voltage, a source connected to a tail current source, and a drain coupled to a drain of a first current source transistor and a source of a first cascode transistor, and

ii. a second input transistor having a gate connected to a second input voltage, a source coupled to the tail current source, and a drain coupled to a drain of a second current source transistor and a source of a second cascode transistor;

(b) a class AB output stage including a pull-up transistor and current mirror circuitry connecting a gate of the pull-up transistor to a drain of the second cascode transistor and a pull-down transistor including a gate connected to a drain of the first cascode transistor;

(c) a first slew boost circuit having an input connected to the drain of the first input transistor and an output connected to the source of the second cascode transistor for amplifying an excess of tail current steered by the first input transistor into the input of the first slew boost circuit over a current flowing in the first current source transistor and applying the amplified excess to boost the slew rate of the class AB output stage in accordance with a first polarity of the difference between the first and second input voltages; and

(d) a second slew boost circuit having an input connected to the drain of the second input transistor and an output connected to the source of the first cascode transistor for amplifying an excess of tail current steered by the second input transistor into the input of the second slew boost circuit over a current flowing in the second current source transistor and applying the amplified excess to boost the slew rate of the class AB output stage in accordance with a second polarity of the difference between the first and second input voltages;

(e) the first slew boost circuit including a first current mirror circuit including a first control transistor having a source connected to a first reference conductor and a gate and drain coupled to the input of the first slew boost circuit and to a gate of a first current mirror output transistor having a source connected to the first reference voltage and a drain coupled to the source of the second cascode transistor, and the second slew boost circuit including a second current mirror circuit including a second control transistor having a source connected to the first reference voltage and a gate and drain coupled to the input of the second slew boost circuit and to a gate of a second current mirror output transistor having a source connected to the first reference voltage and a drain coupled to the source of the first cascode transistor;

(f) the first and second input transistors being N-channel transistors each having a source coupled to a first terminal of a first constant current source and having a second terminal coupled to a second reference voltage.