SXT emergency operation procedure Rev. A: October 14, 1991 S. Tsuneta This memo defines the emergency operation procedure for SXT. This procedure may assume that the only foreseeable SXT problem is the hangup or malfunction caused by RAM corruption(soft error) due to the radiation. The hangup or malfunction caused by RAM soft error is completely recoverable with the following procedure. 1. SXT safehold configration In the emergency situation, your highest priority is to put the SXT in the safehold configration: SHUTTER: CLOSE FILTER B/A: 1/3 (B=1, A=3: photon flood configration) One of these two conditions put SXT in the safe-enough configration. Note: There is a possibility that the MAILBOX status does not reflect the actual hardware configration, when RAM error occurs. It is advisable not to rely on MAILBOX status when STATUS READY ERROR is set, or other status is apparantly wrong. 2. Recovery procedure Put SXT in the safehold configration: _____________________________________ 1 DC A3H SXT CONT MANU (if SXT is in AUTO mode.) [Confirm SXT CONTROL: MANUAL] 2 BC 84H 00H 01H MAILBOX SHUTTER CLOSE(if SHUTTER is OPEN.) [Confirm shutter:OPEN->CLOSE] 3 BC 84H 03H 13H MAILBOX SHUTTER B/A=1/3(if B/A is not 1/3.) [Confirm the filter position] Note: The shutter CLOSE and the filter positioning command may not work, depending on the RAM corruption. Even if you can not verify the status, please proceed to the next step. Reset the SXTE-U micro and RAM patch: _____________________________________ 4 DC 91H HARD RESET (DOUBLE COMMAND) [Confirm micro state:N(ormal)->R(eset)] 5 ====RAM patch sequence(See the appendix)==== The following procedure OPENS THE SHUTTER until you send MAILBOX SHUTTER CLOSE command. You have to reach the SHUTTER CLOSE once initiated the sequence. Judge wheter to start this sequence or not, when the remaining contact time is shorter than 1 minutes. You can request EMERGENCY to KSC, so that we are allowed to send the command unitl the actual loss of the contact. (Normally, we are not allowed to send the commands, if the antenna angle is below 10 degree.) 6 DC 8AH SHUTTER OFF [Confirm D:OFF] 7 DC 85H SHUTTER ON [Confirm D:ON] 8 BC 84H 02H 01H MAILBOX DAY mode [Confirm micro state:R(eset)->N(ormal)] 9 BC 84H 00H 01H MAILBOX SHUTTER CLOSE [Confirm shutter:OPEN->CLOSE] 10 BC 84H 03H 13H MAILBOX SHUTTER B/A=1/3 [Confirm the filter position] ====You established the safehold configration.=== Resume the normal operation: ____________________________ If everything is OK, proceed to the following command. Confirm that SXT starts the exposures. ====Request QT/HIGH or FL/HIGH mode==== 11 DC 6BH SXT PWR AUTO [Confirm SXT POWER CONTROL: AUTO] 12 DC ADH SXT CHK DIS(if SXT (BDR) CHECK status is ENA.) [Confirm SXT BDR CHECK: DIS] 13 DC A2H SXT CONTROL AUTO [Confirm SXT CONTROL: AUTO, and the start of the observation.] Note: If the SXT CONTROL stays on MANUAL, this indicates that the SXTE-J error handling routine automatically set the SXT CONTROL MANUAL, detecting the MAILBOX error flag and/or no status ready resopnse from SXTE-U. Check the error status,and establish the safehold configration. Record all the anomaly found with time in the operation log. 3. Real emergency In case something else happens, although HIGL UNLIKELY, or the system can not be recovered with this procedure, send the following commands after trying to establish the safehold configration: 1 DC 8AH SHUTTER OFF 2 DC 8BH FDE OFF 3 DC 8CH CAMERA OFF 4 DC 89H TEC OFF This still maintains useful information in the SXTE-U RAM for the subsequent failure analysis. However, if necessary, send the following command. 1 DC 80H SXT ALL POWER OFF Appendix RAM patch sequence 1. Start the RAM check software on the mainframe SSOC#1: EX S RAMQL (Hit return without any input for the prompt.) 2. RAM WRITE command sequence The following command sequence is stored in the commanding computer at KSC. However, confirm that the recent RAM code chage in address 46E9H to 07H from 00H is implemented. Note: DC BC ENA(ble) and DC BC EXEC(ute) are not listed here. RAM WRITE: __________ 1 BC 83H 40H 6BH 01H 5CH SXTE-U RAM BUFFER WRITE [Confirm 83H and 406B01H in the command answerback prior to DC EXEC.] Note: BC command code and the first 3 bytes of the BC data area can be checked with DP command answerback. [Confirm RAM BUFFER WRITE answerback after DC EXEC.] 2 BC A5H SXTE-U RAM WRITE [Confirm RAM WRITE answer back] 3 BC 83H 46H 1EH 01H 30H SXTE-U RAM BUFFER WRITE [Confirm 83H and 461E01H in the command answerback prior to DC EXEC.] [Confirm RAM BUFFER WRITE answerback after DC EXEC.] 4 BC A5H SXTE-U RAM WRITE [Confirm RAM WRITE answer back] 5 BC 83H 46H E9H 01H 07H SXTE-U RAM BUFFER WRITE [Confirm 83H and 46E901H in the command answerback prior to DC EXEC.] [Confirm RAM BUFFER WRITE answerback after DC EXEC.] 6 BC A5H SXTE-U RAM WRITE [Confirm RAM WRITE answer back] RAM READ: _________ 7 BC 82H 40H 6BH SXTE-U RAM READ [Confirm RAM READ answerback and that the RAM data appears in RAMQL display.] 8 BC 82H 46H 1EH SXTE-U RAM READ [Confirm RAM READ answerback and that the RAM data appears in RAMQL display.] 9 BC 82H 46H E9H SXTE-U RAM READ [Confirm RAM READ answerback and that the RAM data appears in RAMQL display.] ===Check OK status in the RAMQL display=== If not OK, send DC 91H HARD RESET (DOUBLE COMMAND) and start from the beginning in the RAM PATCH procedure. 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