Machine used : Hopper, 250 MHz, 4MB L2 cache, R10000
4 cpus used
compiler option: -O0 -mp
WARNING: Multiplexing events to project totals--inaccuracy possible
Summary for execution of ./false2_O0
Based on 250 MHz IP27
MIPS R10000 CPU
CPU revision 3.x
Typical Minimum Maximum
Event Counter Name Counter Value Time (sec) Time (sec) Time (sec)
===================================================================================================================
0 Cycles...................................................... 19776534800 79.106139 79.106139 79.106139
16 Cycles...................................................... 19776534800 79.106139 79.106139 79.106139
14 ALU/FPU progress cycles..................................... 1856985280 7.427941 7.427941 7.427941
2 Issued loads................................................ 1558738912 6.234956 6.234956 6.234956
18 Graduated loads............................................. 1432085104 5.728340 5.728340 5.728340
26 Secondary data cache misses................................. 15465200 4.670490 3.053449 5.196307
6 Decoded branches............................................ 1148478944 4.593916 4.593916 4.593916
25 Primary data cache misses................................... 77464160 2.791808 0.873796 2.791808
7 Quadwords written back from scache.......................... 92497152 2.367927 1.565052 2.367927
22 Quadwords written back from primary data cache.............. 24262496 0.373642 0.304737 0.431872
3 Issued stores............................................... 83669120 0.334676 0.334676 0.334676
19 Graduated stores............................................ 81484912 0.325940 0.325940 0.325940
21 Graduated floating point instructions....................... 41746832 0.166987 0.083494 8.683341
31 Store/prefetch exclusive to shared block in scache.......... 11336336 0.045345 0.045345 0.045345
9 Primary instruction cache misses............................ 86400 0.006228 0.001946 0.006228
23 TLB misses.................................................. 7120 0.001939 0.001939 0.001939
10 Secondary instruction cache misses.......................... 4576 0.001382 0.000903 0.001538
24 Mispredicted branches....................................... 25056 0.000142 0.000064 0.000523
4 Issued store conditionals................................... 320 0.000001 0.000001 0.000001
20 Graduated store conditionals................................ 64 0.000000 0.000000 0.000000
1 Issued instructions......................................... 3708187024 0.000000 0.000000 14.832748
5 Failed store conditionals................................... 0 0.000000 0.000000 0.000000
8 Correctable scache data array ECC errors.................... 0 0.000000 0.000000 0.000000
11 Instruction misprediction from scache way prediction table.. 11984 0.000000 0.000000 0.000048
12 External interventions...................................... 13099472 0.000000 0.000000 0.000000
13 External invalidations...................................... 9580848 0.000000 0.000000 0.000000
15 Graduated instructions...................................... 4327306496 0.000000 0.000000 17.309226
17 Graduated instructions...................................... 3518320816 0.000000 0.000000 14.073283
27 Data misprediction from scache way prediction table......... 72640 0.000000 0.000000 0.000291
28 External intervention hits in scache........................ 13095504 0.000000 0.000000 0.000000
29 External invalidation hits in scache........................ 9430736 0.000000 0.000000 0.000000
30 Store/prefetch exclusive to clean block in scache........... 0 0.000000 0.000000 0.000000
Statistics
=========================================================================================
Graduated instructions/cycle................................................ 0.218810
Graduated floating point instructions/cycle................................. 0.002111
Graduated loads & stores/cycle.............................................. 0.076534
Graduated loads & stores/floating point instruction......................... 36.255925
Mispredicted branches/Decoded branches...................................... 0.000022
Graduated loads/Issued loads................................................ 0.918746
Graduated stores/Issued stores.............................................. 0.973895
Data mispredict/Data scache hits............................................ 0.001172
Instruction mispredict/Instruction scache hits.............................. 0.146461
L1 Cache Line Reuse......................................................... 18.538972
L2 Cache Line Reuse......................................................... 4.008934
L1 Data Cache Hit Rate...................................................... 0.948820
L2 Data Cache Hit Rate...................................................... 0.800357
Time accessing memory/Total time............................................ 0.170891
Time not making progress (probably waiting on memory) / Total time.......... 0.906102
L1--L2 bandwidth used (MB/s, average per process)........................... 36.243117
Memory bandwidth used (MB/s, average per process)........................... 43.732384
MFLOPS (average per process)................................................ 0.527732
real 20.368
user 80.451
sys 0.060