| US 7,355,220 B2 | ||
| Array substrate | ||
| Kazuyoshi Omata, Fukaya (Japan); and Makoto Shibusawa, Fukaya (Japan) | ||
| Assigned to Toshiba Matsushita Display Technology Co., Ltd., Tokyo (Japan) | ||
| Filed on Mar. 27, 2006, as Appl. No. 11/389,074. | ||
| Claims priority of application No. 2005-104647 (JP), filed on Mar. 31, 2005; application No. 2005-105096 (JP), filed on Mar. 31, 2005; and application No. 2005-105098 (JP), filed on Mar. 31, 2005. | ||
| Prior Publication US 2006/0220580 A1, Oct. 05, 2006 | ||
| Int. Cl. H01L 33/00 (2006.01); H01L 27/105 (2006.01) | ||
| U.S. Cl. 257—208 [257/390; 257/401; 257/E33.044] | 14 Claims |
| 1. An array substrate comprising an insulating substrate, pixel circuits arranged in a matrix on the insulating substrate,
and video signal lines arranged correspondently with columns which the pixel circuits form, each of the pixel circuits comprising:
a drive transistor whose source is connected to a power supply terminal;
a pixel electrode;
an output control switch connected between a drain of the drive transistor and the pixel electrode;
a selector switch connected between the drain and the video signal line;
a diode-connecting switch including switching elements connected in series between the drain and a gate of the drive transistor;
a first capacitor including an electrode connected to the gate; and
a second capacitor including a first electrode to which two of the switching elements are connected in parallel.
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