US 7,390,752 B2 | ||
Self-aligning patterning method | ||
Shunpu Li, Cambridge (United Kingdom); Thomas Kugler, Cambridge (United Kingdom); Christopher Newsome, Cambridge (United Kingdom); and David Russell, Cambridge (United Kingdom) | ||
Assigned to Seiko Epson Corporation, Tokyo (Japan) | ||
Filed on Oct. 20, 2005, as Appl. No. 11/253,756. | ||
Claims priority of application No. 0427035.1 (GB), filed on Dec. 09, 2004. | ||
Prior Publication US 2006/0128076 A1, Jun. 15, 2006 | ||
Int. Cl. H01L 21/302 (2006.01) |
U.S. Cl. 438—723 [438/719; 438/720; 438/745] | 15 Claims |
1. A method of forming a transistor, comprising:
forming a first conductive layer over a substrate;
forming a first insulating layer over the first conductive layer;
forming a second insulating layer over the first insulating layer;
forming a mask over a first portion of the second insulating layer, the mask being positioned above a first portion of the
first insulating layer, the first portion of the second insulating layer and a first portion of the first conductive layer;
removing a second portion of the first insulating layer, a second portion of the second insulating layer, and a second portion
of the first conductive layer;
forming a third insulating layer over the mask, the third insulating layer covering the first portion of the first insulating
layer, the first portion of the second insulating layer, the first portion of the first conductive layer, and the substrate;
removing a first portion of the third insulating layer in order to make a second portion of the third insulating layer remain
over the substrate;
forming a second conductive layer over the mask and the second portion of the third insulating layer, a first portion of the
second conductive layer being overlapped with the mask, a second portion of the second conductive layer being positioned above
the second portion of the third insulating layer;
removing the first portion of the second insulating layer, the mask and the first portion of the second conductive layer;
and
forming a semiconductor layer over the first portion of the first insulating layer and the second portion of the second conductive
layer.
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