a pull-up PMOS transistor coupled to a high voltage supply terminal VDD and having a gate configured to receive a signal PUP;

a pull-down NMOS transistor arranged between and the pull-up PMOS transistor and a low-voltage supply terminal VSS, wherein the gate of the pull-down NMOS transistor is configured to receive a signal NDN;

a pull-up network coupled to the gate of the pull-up PMOS transistor, wherein the pull-up network comprises:

a first logic gate circuit having a threshold voltage VTHP for an input signal PPUP and configured to produce at least a portion of PUP;

a first Schmitt trigger circuit configured to receive PUP as an input and output a signal FPUP, wherein the first Schmitt trigger circuit has a switching threshold voltage VSTP for PUP; and

a second logic gate circuit having a threshold voltage substantially at VTHP for the input signal PPUP and configured to produce at least a portion of PUP, wherein the second logic circuit is enable controlled by the signal FPUP; and

a pull-down network coupled to the gate of the pull-down NMOS transistor, wherein the pull-down network comprises:

a third logic gate circuit having a threshold voltage VTHN for an input signal PNDN and configured to produce at least a portion of NDN;

a second Schmitt trigger circuit configured to receive NDN as an input and output a signal FNDN, wherein the second Schmitt trigger circuit has a switching threshold voltage VSTN for NDN; and

a fourth logic gate circuit having a threshold voltage substantially at VTHN and an output connected to the gate of the pull-down NMOS transistor, wherein the fourth logic circuit is enable controlled by the signal FNDN.